In many digital electronic circuits, complementary clock signals having a mutually inverse relationship are required. Because the operating speed of the electronic circuits gradually increases, clock signals having an exactly inverse relation in the time axis are required.
As illustrated in FIG. 1A, a conventional CMOS complementary clock generator for generating complementary clocks includes: a same-phase path having two serially connected CMOS inverters Inv1 and Inv2 for outputting a clock signal with a phase the same as that of an input clock; and an opposite-phase path having three serially-connected CMOS inverters Inv3, Inv4 and Inv5 for outputting a clock signal with a phase opposite to that of the input clock. The same-phase path is formed by serially connecting an even number of inverters, while the opposite-phase path is formed by serially connecting an odd number of inverters.
As illustrated in FIG. 1B, each of CMOS inverters Inv1, Inv2, Inv3, Inv4 and Inv5 is constituted such that PMOS transistor MP1 and NMOS transistor MN1 are serially connected, with the gates of PMOS transistor MP1 and NMOS transistor MN1 connected to receive an input signal, and an output is outputted through a connection point of the sources and drains of the transistors as illustrated.
This circuit operates in the following manner. For example, if input clock signal Clkin has pulses with a duty cycle of 50%, same-phase output clock signal Clk, with pulses having passed through the same-phase path, i.e., inverters Inv1 and Inv2, have the same phase as that of the input clock, while opposite-phase output clock signal /Clk, with pulses having passed through the opposite-phase path, i.e., inverters Inv3, Inv4 and Inv5, have a phase opposite to that of the input clock. Therefore, the clocks have a duty cycle of 50%, and they cross each other at a point of 50%.
If precise complementary clocks having opposite phases at the same timing point are to be formed, the delay of the same-phase path and the opposite-phase path has to be the same, and the number of the inverters of the opposite-phase path has to be larger than that of the inverters of the same-phase path by one. Therefore, the size of the inverters of the opposite-phase path is made to be larger than that of the inverters of the same-phase path, so that the delay of each of the inverters of the opposite-phase path would be smaller than the delay of each of the inverters of the same-phase path. Thus the total delay required in passing through the opposite-phase path is made to be same as the total delay required in passing through the same-phase path.
Generally, the loads of clock signals Clk and /Clk are the same, and the inverters of the opposite-phase path are designed to be bigger than the inverters of the same-phase path. Due to instability of the manufacturing process, the actual sizes of the CMOS inverters are not exactly formed as designed, but instead deviate from the intended design. Therefore, the ratios of the channel widths to the channel lengths of the transistors, i.e., W/L ratios, become different from the intended design. Further, the delay varies in accordance with variations of operating temperature, and, therefore, even if the two paths are matched in the normal operation, the delay can become different if the operating conditions are even slightly different.
As a result, viewed from the time axis, the two complementary clocks are not exactly of an opposite relation, but instead one of them lags behind the other, thereby forming a varying wave pattern. This phenomenon occurs frequently. Further, under certain operating conditions, after maintaining an exactly opposite relationship, if the operating conditions vary even slightly, then a deviating wave pattern is produced.
The basic cause for this phenomenon is as follows. The circuit elements forming the two paths of the same and opposite phases are asymmetrically provided. That is, in the case of the same-phase path, two (or an even number of) inverters form the signal transfer path, while in the case of the opposite-phase path, three (or an odd number of) inverters form the signal transfer path. That is the two paths pass through different kinds of transistors or different numbers of transistors.